Design Compiler

Design Compiler is a product of Synopsys that compiles and optimises (in terms of silicon area and maximum clock frequency) high-level electronic circuit descriptions specified by restricted sub-languages of either Verilog or VHDL, into a gate-level netlist representation of a circuit. This procedure is an example of logic synthesis.

Design Compiler uses language templates to determine what hardware is to be implied. The templates below show some of the basic transforms DC uses.

// Basic D flip flop
reg q;
always @(posedge clk)
  q <= d;

// Basic  D flip flop with Asynchronous reset
always @(posedge clk or posedge reset)
  if(reset)
    q<= 1'b0;
  else
    q<= d;

// Basic D flip flop with both Asynch Reset and Set
always @(posedge clk or posedge reset or posedge set)
  if(reset)
    q <= 1'b0;
  else
  if(set)
    q <= 1'b1;
  else
    q <= d;

// Basic latch
always @(enable)
  if(enable)
    q = d;

// Basic mux
always @(sel or a or b)
  if(sel)
    q = a;
  else
    q = b;