Design Rules Checking (DRC) is the area of Electronic Design Automation software that concerns itself with checking if rules set by physical manufacturers of chips are satisfied in particular chip designs.
DRC software usually takes as input chip design in GDSII standard format.
Design Rules are expressed as mathematical formulas with boolean, connectivity, and geometrical operations taking as arguments layers of material in chips as boolean functions and producing as outputs various violations found in design. Examples of operations: AND, NOT, CONNECTED, INSIDE, EXTERNAL.
Design Rules are set by physical manufacturers like TSMC, IBM, Intel and significantly different for each of them. They change with every major improvement in manufacturing process. Particularly with every level of scaling (further miniaturization) Design Rules become significantly more complex.
Every DRC product defines some language to describe the operations needed to be performed in DRC.
Major products in DRC area of EDA are:
- Calibre by Mentor Graphics having 80% (?) of the market. Calibre replaced Dracula in mid-1990s.
- Dracula by Cadence Design Systems having 10% (?) of the market. Although Calibre dominates Dracula still has small but persistant market share.
Some semiconductor companies have their own proprietary DRC software.
DRC is very resource-intense. Customers often have to wait up to a week to get the result of DRC check for modern designs.
DRC products are used primarily by semiconductor companies developing chip designs. But small part of the market is comprised from companies developing standard cell libraries to verify compliance of their products with Design Rules.
Estimated annual sales of DRC software are in $200-$300 million range.