The Pluribus multiprocessor was an early multi-processor computer designed by BBN for use as a packet switch in the ARPANET. Its design later influenced the BBN Butterfly computers.
The Pluribus had its beginnings in 1972 when the need for a second-generation interface message processor (IMP) became apparent. At that time, the BBN had already installed IMPs at more than thirty-five ARPANET sites. These IMPs were Honeywell 316 and 516 minicomputers. The network was growing rapidly in several dimensions: number of nodes, hosts, and terminals; volume of traffic; and geographic coverage (including plans, now realized, for satellite extensions to Europe and Hawaii).
A goal was established to design a modular machine which, at its lower end, would be smaller and less expensive than the 316's and 516's while being expandable in capacity to provide ten times the bandwidth of, and capable of servicing five times as many input-output (I/O) devices as, the 516. Related goals included greater memory addressing capability and increased reliability.
The designers decided on a multiprocessor approach because of its promising potential for modularity, for cost per performance advantages, for reliability, and because the IMP packet switch algorithms were clearly suitable for parallel processing by independent processors.
References
S. M. Ornstein, William R. Crowther, M. F. Kraley. R. D. Bressler, A. Michel, Frank E. Heart, "Pluribus - A reliable multiprocessor", p. 551, AFIPS vol 44, 1975.
D. Katsuki, E. S. Elsam, W. F. Mann, E. S. Roberts, J. C. Robinson, F. S. Skowronski, E. W. Wolf, "Pluribus-An Operational Fault-Tolerant Multiprocessor", Proc. IEEE, vol. 66, no. 10, October 1978, pp. 1,146-1,159.